Isometric Test Data Compression

Amit Kumar; Mark Kassab; Elham Moghaddam; Nilanjan Mukherjee; Janusz Rajski; Sudhakar M Reddy; Jerzy Tyszer; Chen Wang

doi:10.1109/TCAD.2015.2432133

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Journal article

Peer reviewed

Isometric Test Data Compression

Amit Kumar, Mark Kassab, Elham Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M Reddy, Jerzy Tyszer and Chen Wang

IEEE transactions on computer-aided design of integrated circuits and systems, Vol.34(11), pp.1847-1859

11/2015

DOI: 10.1109/TCAD.2015.2432133

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Abstract

This paper introduces a novel test data compression scheme, which is primarily devised for low-power test applications. It is based on a fundamental observation that in addition to low test cube fill rates, a very few specified bits, necessary to detect a fault, are actually irreplaceable, whereas the remaining ones can be placed in alternative locations (scan cells). The former assignments are used to create residual test cubes and, subsequently, test templates. They control a power-aware decompressor and guide automatic test pattern generation to produce highly compressible test patterns through finding alternative assignments. The proposed approach reduces, in a user-controlled manner, scan shift-in switching rates with minimal hardware modifications. It also elevates compression ratios to values typically unachievable through conventional low-power reseeding-based solutions. Experimental results obtained for large industrial designs illustrate feasibility of the proposed test scheme and are reported herein.

Automatic test pattern generation

Circuit faults

Design for testability

embedded deterministic test

Encoding

Logic gates

low power test

scan-based designs

Switches

System-on-chip

test compression

Test data compression

Details

Title: Subtitle: Isometric Test Data Compression
Creators: Amit Kumar - Synopsys
Mark Kassab - Mentor Graphics
Elham Moghaddam - Mentor Graphics
Nilanjan Mukherjee - Mentor Graphics
Janusz Rajski - Mentor Graphics
Sudhakar M Reddy - University of Iowa
Jerzy Tyszer - Poznań University of Technology
Chen Wang - Mentor Graphics
Resource Type: Journal article
Publication Details: IEEE transactions on computer-aided design of integrated circuits and systems, Vol.34(11), pp.1847-1859
DOI: 10.1109/TCAD.2015.2432133
ISSN: 0278-0070
eISSN: 1937-4151
Publisher: IEEE
Grant note: DS-811/14 / Polish Ministry of Science and Higher Education
Language: English
Date published: 11/2015
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197271202771

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