Long and short covering edges in combination logic circuits

Wing-Ning Li; Sudhakar M Reddy; Sartaj Sahni

doi:10.1109/43.62769

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Long and short covering edges in combination logic circuits

Journal article

Peer reviewed

Long and short covering edges in combination logic circuits

Wing-Ning Li, Sudhakar M Reddy and Sartaj Sahni

IEEE transactions on computer-aided design of integrated circuits and systems, Vol.9(12), pp.1245-1253

12/1990

DOI: 10.1109/43.62769

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Abstract

The polynomial time algorithm obtained earlier by the authors is extended to find a minimal cardinality path set that long covers each lead or gate input of a digital logic circuit. It is shown how to find, in polynomial time, a minimal cardinality set MinMaxSP for a given combinational logic circuit. Combinational circuit verification is used to verify the sequential circuit delays.< >

Circuit testing

Combinational circuits

Delay

Electrical fault detection

Flip-flops

Logic circuits

Pipelines

Sequential circuits

Signal design

Timing

Details

Title: Subtitle: Long and short covering edges in combination logic circuits
Creators: Wing-Ning Li - University of Arkansas
Sudhakar M Reddy - University of Iowa
Sartaj Sahni - University of Florida
Resource Type: Journal article
Publication Details: IEEE transactions on computer-aided design of integrated circuits and systems, Vol.9(12), pp.1245-1253
Publisher: IEEE
DOI: 10.1109/43.62769
ISSN: 0278-0070
eISSN: 1937-4151
Language: English
Date published: 12/1990
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197306402771

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