NEST: a nonenumerative test generation method for path delay faults in combinational circuits

I Pomeranz; S.M Reddy; P Uppaluri

doi:10.1109/43.476581

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NEST: a nonenumerative test generation method for path delay faults in combinational circuits

Journal article

Peer reviewed

NEST: a nonenumerative test generation method for path delay faults in combinational circuits

I Pomeranz, S.M Reddy and P Uppaluri

IEEE transactions on computer-aided design of integrated circuits and systems, Vol.14(12), pp.1505-1515

12/1995

DOI: 10.1109/43.476581

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Abstract

A test generation procedure for path delay faults is proposed that targets all path delay faults in the circuit-under-test. The procedure overcomes the difficulties in handling the exorbitant numbers of path delay faults in practical circuits by using a nonenumerative method of considering faults that never explicitly targets any specific path delay fault. Experimental results demonstrate the effectiveness of the method in deriving tests to detect very large numbers of path delay faults.

Circuit faults

Circuit simulation

Circuit testing

Combinational circuits

Delay estimation

Design automation

Electrical fault detection

Fault detection

Labeling

Propagation delay

Details

Title: Subtitle: NEST: a nonenumerative test generation method for path delay faults in combinational circuits
Creators: I Pomeranz - University of Iowa
S.M Reddy - University of Iowa
P Uppaluri - University of Iowa
Resource Type: Journal article
Publication Details: IEEE transactions on computer-aided design of integrated circuits and systems, Vol.14(12), pp.1505-1515
Publisher: IEEE
DOI: 10.1109/43.476581
ISSN: 0278-0070
eISSN: 1937-4151
Language: English
Date published: 12/1995
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984196969802771

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