Journal article
On Concurrent Test of Core-Based SOC Design
Journal of electronic testing, Vol.18(4), pp.401-414
08/2002
DOI: 10.1023/A:1016541407006
Abstract
In this paper, a method to solve the resource allocation and test scheduling problems together in order to achieve concurrent test for core-based System-On-Chip (SOC) designs is presented. The primary objective for concurrent SOC test is to reduce test application time under the constraints of SOC pins and peak power consumption. The methodology used in this paper is not limited to any specific Test Access Mechanism (TAM). Additionally, it can also be applied to SOC budgeting at design phase to predict a tradeoff between test application time and SOC pins needed. The contribution of this paper is the formulation of the problem as a well-known 2-dimensional bin-packing problem. A best-fit heuristic algorithm is adopted to achieve optimal solution.
Details
- Title: Subtitle
- On Concurrent Test of Core-Based SOC Design
- Creators
- Yu Huang - Mentor GraphicsWu-Tung Cheng - Mentor GraphicsChien-Chung Tsai - Mentor GraphicsNilanjan Mukherjee - Mentor GraphicsOmer Samman - Mentor GraphicsYahya Zaidan - Mentor GraphicsSudhakar Reddy - University of Iowa
- Resource Type
- Journal article
- Publication Details
- Journal of electronic testing, Vol.18(4), pp.401-414
- DOI
- 10.1023/A:1016541407006
- ISSN
- 0923-8174
- eISSN
- 1573-0727
- Publisher
- Kluwer Academic Publishers
- Language
- English
- Date published
- 08/2002
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197912902771
Metrics
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