Journal article
On Selecting Testable Paths in Scan Designs
Journal of electronic testing, Vol.19(4), pp.447-456
08/2003
DOI: 10.1023/A:1024648227669
Abstract
We propose an efficient method to select a minimal set of testable paths in scan designs, such that every line in the circuit is covered by at least one of the longest testable paths that contain it (if there are any). The proposed path selection approach is based on a stepwise path expansion procedure that uses delay information and compact information about untestable paths to select longest paths while avoiding untestable paths. Techniques called delay analysis and delay-constrained path expansion are used to speedup the selection of paths to test. Compared to earlier approaches, the proposed approach is fast and it is guaranteed to find testable paths. Additionally the procedure also derives tests for the selected paths. Experimental results for ISCAS89 benchmark circuits using standard scan and broadside testing are presented to demonstrate the effectiveness of the proposed method.
Details
- Title: Subtitle
- On Selecting Testable Paths in Scan Designs
- Creators
- Yun Shao - University of IowaSudhakar Reddy - University of IowaIrith Pomeranz - Purdue University West LafayetteSeiji Kajihara - Kyushu Institute of Technology
- Resource Type
- Journal article
- Publication Details
- Journal of electronic testing, Vol.19(4), pp.447-456
- DOI
- 10.1023/A:1024648227669
- ISSN
- 0923-8174
- eISSN
- 1573-0727
- Publisher
- Kluwer Academic Publishers
- Language
- English
- Date published
- 08/2003
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197226102771
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