Journal article
On Test Generation With Test Vector Improvement
IEEE transactions on computer-aided design of integrated circuits and systems, Vol.29(3), pp.502-506
03/2010
DOI: 10.1109/TCAD.2010.2041853
Abstract
We investigate the introduction of a new step, referred to as test vector improvement, into test generation processes. After a fully specified test vector or a partially specified test cube t is generated at an arbitrary iteration of the test generation process, the test vector improvement step modifies t so as to increase the number of yet-undetected target faults that t detects. This is done in this paper using a simulation-based process. We show that even if t was generated using dynamic test compaction heuristics, it is possible to improve t further. When t is partially specified to accommodate test data compression, the test vector improvement step does not change the number of unspecified bits of t. The final result is a smaller test set and/or a higher fault coverage (if the test generation process does not detect all the detectable faults). © 2006 IEEE.
Details
- Title: Subtitle
- On Test Generation With Test Vector Improvement
- Creators
- Irith Pomeranz - Purdue University West LafayetteSudhakar M Reddy - University of Iowa
- Resource Type
- Journal article
- Publication Details
- IEEE transactions on computer-aided design of integrated circuits and systems, Vol.29(3), pp.502-506
- DOI
- 10.1109/TCAD.2010.2041853
- ISSN
- 0278-0070
- eISSN
- 1937-4151
- Language
- English
- Date published
- 03/2010
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197520002771
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