On achieving minimal size test sets for scan designs

Sudhakar M Reddy; Zhuo Zhang

doi:10.1515/itit-2013-1039

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On achieving minimal size test sets for scan designs

Journal article

Peer reviewed

On achieving minimal size test sets for scan designs

Sudhakar M Reddy and Zhuo Zhang

Information technology (Munich, Germany), Vol.56(4), pp.150-156

08/28/2014

DOI: 10.1515/itit-2013-1039

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Abstract

In this paper we provide experimental evidence that digital VLSI circuit designs using an earlier proposed DFT method called may be testable using fewer tests than needed for unsegmented scan versions of the same designs. Results on ISCAS 89 benchmark circuits show that the test set sizes for detecting stuck-at faults in segmented scan designs may be lower than the lower bounds on test set sizes for unsegmented scan versions. Thus, segmented scan design may be a way to achieve minimal test set sizes for digital VLSI circuits.

ACM CCS→Hardware→Hardware test→Design for testability

minimal test sets

scan design

segmented scan design

stuck-at-faults

test-pattern generation

Details

Title: Subtitle: On achieving minimal size test sets for scan designs
Creators: Sudhakar M Reddy - University of Iowa
Zhuo Zhang - 2 I.M. Systems Group, Rockville, MD, USA
Resource Type: Journal article
Publication Details: Information technology (Munich, Germany), Vol.56(4), pp.150-156
Publisher: De Gruyter Oldenbourg
DOI: 10.1515/itit-2013-1039
ISSN: 1611-2776
eISSN: 2196-7032
Number of pages: 7
Language: English
Date published: 08/28/2014
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197295702771

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