On determining symmetries in inputs of logic circuits

I Pomeranz; S.M Reddy

doi:10.1109/43.329273

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On determining symmetries in inputs of logic circuits

Journal article

Peer reviewed

On determining symmetries in inputs of logic circuits

I Pomeranz and S.M Reddy

IEEE transactions on computer-aided design of integrated circuits and systems, Vol.13(11), pp.1428-1434

11/1994

DOI: 10.1109/43.329273

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Abstract

We propose a method for computing maximal sets of symmetric inputs in logic circuits, using a test generation procedure for single stuck-at faults. The method is enhanced by a heuristic that can be used to identify nonsymmetric inputs and thus reduce the number of inputs for which test generation has to be carried out. We show the relevance of the problem to input matching for design diagnosis and for technology mapping. Experimental results demonstrate the effectiveness of the proposed procedures.< >

Circuit faults

Circuit testing

Cities and towns

Impedance matching

Libraries

Logic circuits

Logic design

Logic functions

Logic testing

Details

Title: Subtitle: On determining symmetries in inputs of logic circuits
Creators: I Pomeranz - University of Iowa
S.M Reddy - University of Iowa
Resource Type: Journal article
Publication Details: IEEE transactions on computer-aided design of integrated circuits and systems, Vol.13(11), pp.1428-1434
Publisher: IEEE
DOI: 10.1109/43.329273
ISSN: 0278-0070
eISSN: 1937-4151
Language: English
Date published: 11/1994
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197353302771

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