Journal article
On fault simulation for synchronous sequential circuits
IEEE transactions on computers, Vol.44(2), pp.335-340
02/1995
DOI: 10.1109/12.364543
Abstract
We investigate the considerations to be employed in designing a fault simulator for synchronous sequential circuits described at the gate level. Three testing strategies and three methods of handling unknown state variable values are considered. Every combination of a test strategy and a method of handling unknown state variable values defines a different fault simulation procedure. Experimental results are presented to demonstrate the different fault coverage levels achievable by the various procedures. Based on these results, a fault simulation procedure that combines the various considerations is proposed.< >
Details
- Title: Subtitle
- On fault simulation for synchronous sequential circuits
- Creators
- I Pomeranz - University of IowaS.M Reddy - University of Iowa
- Resource Type
- Journal article
- Publication Details
- IEEE transactions on computers, Vol.44(2), pp.335-340
- Publisher
- IEEE
- DOI
- 10.1109/12.364543
- ISSN
- 0018-9340
- eISSN
- 1557-9956
- Language
- English
- Date published
- 02/1995
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197546402771
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