Journal article
On masking of redundant faults in synchronous sequential circuits with design-for-testability logic
IEEE transactions on computer-aided design of integrated circuits and systems, Vol.24(2), pp.288-294
02/2005
DOI: 10.1109/TCAD.2004.840551
Abstract
Design for testability (DFT) for synchronous sequential circuits causes redundant faults in the original circuit to be detectable in the circuit with DFT logic. It has been argued that such faults should not be detected in order to avoid reducing the yield unnecessarily. In this paper, we propose to deal with such faults by masking (or ignoring) their fault effects when they appear on the circuit outputs. This should be done without masking the detection of other faults of the original circuit, which need to be detected. To investigate the extent to which this can be accomplished, we describe a procedure for masking the effects of redundant faults of the original circuit under a given test set generated for the circuit with DFT logic. The procedure attempts to maximize the number of redundant faults that are masked while minimizing (or holding to zero) the number of masked faults among the faults that should be detected.
Details
- Title: Subtitle
- On masking of redundant faults in synchronous sequential circuits with design-for-testability logic
- Creators
- Irith Pomeranz - Purdue University West LafayetteSudhakar M Reddy
- Resource Type
- Journal article
- Publication Details
- IEEE transactions on computer-aided design of integrated circuits and systems, Vol.24(2), pp.288-294
- DOI
- 10.1109/TCAD.2004.840551
- ISSN
- 0278-0070
- eISSN
- 1937-4151
- Publisher
- IEEE
- Language
- English
- Date published
- 02/2005
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197446402771
Metrics
5 Record Views