Sign in
On maximizing the fault coverage for a given test length limit in a synchronous sequential circuit
Journal article   Peer reviewed

On maximizing the fault coverage for a given test length limit in a synchronous sequential circuit

Irith Pomeranz and Sudhakar M Reddy
IEEE transactions on computers, Vol.53(9), pp.1121-1133
09/2004
DOI: 10.1109/TC.2004.63

View Online

Abstract

Circuit testing Combinational logic circuits Fault diagnosis Index Terms- Synchronous sequential circuits Logic circuit testing Sequential logic circuits test application time test compaction

Details

Metrics

Logo image