On path selection in combinational logic circuits

Wing-Ning Li; Sudhakar Reddy; Sartaj K Sahni

doi:10.1109/43.21819

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On path selection in combinational logic circuits

Journal article

Peer reviewed

On path selection in combinational logic circuits

Wing-Ning Li, Sudhakar Reddy and Sartaj K Sahni

IEEE transactions on computer-aided design of integrated circuits and systems, Vol.8(1), pp.56-63

01/1989

DOI: 10.1109/43.21819

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Abstract

In order to ascertain correct operation of digital logic circuits it is necessary to verify correct functional operation as well as correct operation at desired clock rates. To ascertain correct operation at desired clock rates, it is verified that signal propagation delays along a set of selected paths fall within allowed limits by applying appropriate stimuli. It has previously been suggested that an appropriate set of paths to test would be the one that includes at least one path, with maximum modeled delay, for each circuit lead or gate input. Here, algorithms to select such sets of paths with minimum cardinality are given.< >

Circuit testing

Cities and towns

Clocks

Combinational circuits

Contracts

Costs

Instruments

Logic circuits

Propagation delay

Terminology

Details

Title: Subtitle: On path selection in combinational logic circuits
Creators: Wing-Ning Li - Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
Sudhakar Reddy - University of Iowa
Sartaj K Sahni - University of Minnesota
Resource Type: Journal article
Publication Details: IEEE transactions on computer-aided design of integrated circuits and systems, Vol.8(1), pp.56-63
DOI: 10.1109/43.21819
ISSN: 0278-0070
eISSN: 1937-4151
Publisher: IEEE
Language: English
Date published: 01/1989
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197427502771

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