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On reducing test application time for scan circuits using limited scan operations and transfer sequences
Journal article   Peer reviewed

On reducing test application time for scan circuits using limited scan operations and transfer sequences

Yonsang Cho, Irith Pomeranz and Sudhakar M Reddy
IEEE transactions on computer-aided design of integrated circuits and systems, Vol.24(10), pp.1594-1605
10/2005
DOI: 10.1109/TCAD.2005.852285

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Abstract

Application software Circuit testing Cities and towns Combinational circuits Compaction Costs Flip-flops Life testing Limited scan operation Logic testing scan circuit Sequential analysis static compaction test application time reduction

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