On the Design of Logic Networks with Redundancy and Testability Considerations

R Dandapani; S.M Reddy

doi:10.1109/T-C.1974.223821

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On the Design of Logic Networks with Redundancy and Testability Considerations

Journal article

Peer reviewed

On the Design of Logic Networks with Redundancy and Testability Considerations

R Dandapani and S.M Reddy

IEEE transactions on computers, Vol.C-23(11), pp.1139-1149

11/1974

DOI: 10.1109/T-C.1974.223821

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Abstract

The presence of redundancy in combinational networks increases the cardinality of the test set to detect all stuck-at-faults. A solution to this problem is to identify and remove all redundancies in the networks before deriving test sets. It is shown in this paper that the identification of redundancy in arbitrary combinational networks is an extremely tedious problem.

Combinational networks

logic design

prime trees

redundancy

stuck-at-faults

testing

Details

Title: Subtitle: On the Design of Logic Networks with Redundancy and Testability Considerations
Creators: R Dandapani - University of Iowa
S.M Reddy
Resource Type: Journal article
Publication Details: IEEE transactions on computers, Vol.C-23(11), pp.1139-1149
Publisher: IEEE
DOI: 10.1109/T-C.1974.223821
ISSN: 0018-9340
eISSN: 1557-9956
Language: English
Date published: 11/1974
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197352902771

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