On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits

Jan Burchard; Dominik Erb; Sudhakar M Reddy; Adit D Singh; Bernd Becker

doi:10.1109/TCAD.2017.2772825

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On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits

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On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits

Jan Burchard, Dominik Erb, Sudhakar M Reddy, Adit D Singh and Bernd Becker

IEEE transactions on computer-aided design of integrated circuits and systems, Vol.37(10), pp.2152-2165

10/2018

DOI: 10.1109/TCAD.2017.2772825

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Abstract

Opens are known to be one of the predominant defects in nanoscale technologies. With an increasing number of complex cells in today's very large-scale integration designs intracell opens are becoming a larger and larger problem. Typically, these defects are modeled by transistor stuck-off faults (TSOFs) and assumed to be detected by transition delay fault (TDF) timing tests. However, tests for TDF fail to detect a high percentage of TSOFs and even tools that target them directly are not sufficient to screen all open defects. Furthermore, generated tests might be invalidated in case hazards and charge-sharing are not properly considered. In this paper, we present a waveform-accurate SAT-based automatic test pattern generation (ATPG) framework to tackle these problems. The proposed method not only allows for the generation of tests that are robust against hazards and charge-sharing, it can also be used to generate tests for faults only detectable by hazard-based activation-and hence even increase the fault coverage beyond state-of-the-art cell-aware tests. Our experimental results for the largest ITC'99, IWLS 2005 as well as larger industrial circuits mapped to the state-of-the-art NanGate 45-nm as well as NanGate 15-nm cell library using complex cells show the high efficiency and scalability of the proposed method. For example, the results show that without properly considering hazards and charge-sharing up to 17.9% of the generated tests could be invalidated. In addition, hazard-activated ATPG allows to detect an additional 10.1% of conventionally undetectable faults that could result in a very significant defective parts per million improvement.

Automatic test pattern generation

charge-sharing

Circuit faults

circuit testing

Delays

Hazards

Libraries

Logic gates

Robustness

SAT

transistor stuck-off

transistor stuck-open (TSOP)

Transistors

Details

Title: Subtitle: On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits
Creators: Jan Burchard - University of Freiburg
Dominik Erb - Infineon Technologies
Sudhakar M Reddy - University of Iowa
Adit D Singh - Auburn University
Bernd Becker - University of Freiburg
Resource Type: Journal article
Publication Details: IEEE transactions on computer-aided design of integrated circuits and systems, Vol.37(10), pp.2152-2165
Publisher: IEEE
DOI: 10.1109/TCAD.2017.2772825
ISSN: 0278-0070
eISSN: 1937-4151
Grant note: NSF CCF 1319529; NSF CCF 1527049 / National Science Foundation (10.13039/100000001)
Language: English
Date published: 10/2018
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197182602771

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