Journal article
On the design of fault-tolerant two-dimensional systolic arrays for yield enhancement
IEEE transactions on computers, Vol.38(4), pp.515-525
04/1989
DOI: 10.1109/12.21144
Abstract
The authors propose a unified approach to the design of the fault-tolerant systolic arrays incorporating design for testability, a testing scheme, a reconfiguration algorithm, time-complexity analysis of the proposed reconfiguration algorithm, and yield analysis. A main feature of the proposed designs is that multiple processing elements in a 2-D array can be tested simultaneously, thus reducing the testing time significantly. Another feature is that with the introduction of delay registers, the proposed reconfiguration algorithm reconfigures a faulty 2-D systolic array into a fault-free array without reducing throughput. The overall aim is to provide a design for a 2-D systolic array that produces high yield in VLSI/WSI implementations.< >
Details
- Title: Subtitle
- On the design of fault-tolerant two-dimensional systolic arrays for yield enhancement
- Creators
- Jung Hwan Kim - Center for Adv. Comput. Studies, Univ. of SW Louisiana, Lafayette, LA, USASudhakar M Reddy - University of Iowa
- Resource Type
- Journal article
- Publication Details
- IEEE transactions on computers, Vol.38(4), pp.515-525
- Publisher
- IEEE
- DOI
- 10.1109/12.21144
- ISSN
- 0018-9340
- eISSN
- 1557-9956
- Language
- English
- Date published
- 04/1989
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197348502771
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