Journal article
On the effectiveness of residue code checking for parallel two's complement multipliers
IEEE transactions on very large scale integration (VLSI) systems, Vol.4(2), pp.227-239
1996
DOI: 10.1109/92.502194
Abstract
The effectiveness of residue code checking for online error detection in parallel two's complement multipliers has only up until now been evaluated experimentally for few architectures. In this paper a formal analysis is given for most of the current multiplication schemes. Based on this analysis it is shown which check bases are appropriate, and how the original scheme has to be extended for complete error detection at the input registers and Booth recoding circuitry. In addition, we argue that the hardware overhead for checking can be reduced by approximately one half if a small latency in error detection is acceptable. Schemes for structuring the checking logic in order to guarantee it to be self-testing, and thus achieve the totally self-checking goal for the overall circuit, are also derived. © 1996 IEEE.
Details
- Title: Subtitle
- On the effectiveness of residue code checking for parallel two's complement multipliers
- Creators
- U Sparmann - University of IowaS. M Reddy - University of Iowa
- Resource Type
- Journal article
- Publication Details
- IEEE transactions on very large scale integration (VLSI) systems, Vol.4(2), pp.227-239
- Publisher
- Institute of Electrical and Electronics Engineers
- DOI
- 10.1109/92.502194
- ISSN
- 1063-8210
- eISSN
- 1557-9999
- Language
- English
- Date published
- 1996
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197436102771
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