Journal article
On the fault coverage of gate delay fault detecting tests
IEEE transactions on computer-aided design of integrated circuits and systems, Vol.16(1), pp.78-94
1997
DOI: 10.1109/43.559333
Abstract
This paper addresses the problem of obtaining accurate fault coverages for the gate delay fault model. For a gate delay fault, it is not sufficient to only find a test. One also has to accurately determine the size of the fault detected. We first show that previous methodologies for determining gate delay fault coverages have certain limitations. A method is then investigated to determine all the possible ranges of detected fault sizes, using the traditional fixed sampling time approach. However, with the constraints of a realistic inertial delay model, it is then shown that it might still not be possible to achieve the coverages required to guarantee circuit operation without malfunctions. A new and more realistic delay model is proposed to obtain true fault coverages that extend up to the actual circuit slacks whenever possible. An alternate test application strategy, involving the usage of varying sampling times, is also proposed to further enhance the actual fault coverages obtained under the proposed delay model. Results of experiments performed to evaluate these methods are given. © 1997 IEEE.
Details
- Title: Subtitle
- On the fault coverage of gate delay fault detecting tests
- Creators
- A. K Pramanick - Nextwave Design Automation Inc., San Jose, CA, USAS. M Reddy - University of Iowa
- Resource Type
- Journal article
- Publication Details
- IEEE transactions on computer-aided design of integrated circuits and systems, Vol.16(1), pp.78-94
- Publisher
- Institute of Electrical and Electronics Engineers
- DOI
- 10.1109/43.559333
- ISSN
- 0278-0070
- eISSN
- 1937-4151
- Language
- English
- Date published
- 1997
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197207602771
Metrics
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