Journal article
Procedures for static compaction of test sequences for synchronous sequential circuits
IEEE transactions on computers, Vol.49(6), pp.596-607
06/2000
DOI: 10.1109/12.862219
Abstract
We propose three static compaction techniques for test sequences of synchronous sequential circuits. We apply the proposed techniques to test sequences generated for benchmark circuits by various test generation procedures. The results show that the test sequences generated by all the test generation procedures considered can be significantly compacted. The compacted sequences thus have shorter test application times and smaller memory requirements. As a by-product, the fault coverage is sometimes increased as well. Additionally, the ability to significantly reduce the length of the test sequences indicates that it may be possible to reduce test generation time if superfluous input vectors are not generated.
Details
- Title: Subtitle
- Procedures for static compaction of test sequences for synchronous sequential circuits
- Creators
- I Pomeranz - University of IowaS.M Reddy - University of Iowa
- Resource Type
- Journal article
- Publication Details
- IEEE transactions on computers, Vol.49(6), pp.596-607
- Publisher
- IEEE
- DOI
- 10.1109/12.862219
- ISSN
- 0018-9340
- eISSN
- 1557-9956
- Language
- English
- Date published
- 06/2000
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197196102771
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