Reliable sizing of power networks in VLSI circuits

S Chowdhury; J. S Barkatullah

doi:10.1016/0010-4485(92)90046-D

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Reliable sizing of power networks in VLSI circuits

Journal article

Peer reviewed

Reliable sizing of power networks in VLSI circuits

S Chowdhury and J. S Barkatullah

Computer aided design, Vol.24(6), pp.291-300

1992

DOI: 10.1016/0010-4485(92)90046-D

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Abstract

The paper deals with sizing power/ground nets in integrated circuits. Certain reliability constraints such as voltage drop and metal migration are considered. These reliability constraints exist at the lowest level of physical design, and cannot be overcome by techniques such as fault-tolerant design or redundancy at the higher levels. The widths of the power/ground nets are determined subject to the assumed constraints. An attempt is made to reduce the metal area required. Experimental results for examples and runtimes are included. © 1992.

Applied Sciences

Software

Computer aided design

Computer science; control theory; systems

Exact sciences and technology

Details

Title: Subtitle: Reliable sizing of power networks in VLSI circuits
Creators: S Chowdhury - University of Iowa
J. S Barkatullah - University of Iowa
Resource Type: Journal article
Publication Details: Computer aided design, Vol.24(6), pp.291-300
DOI: 10.1016/0010-4485(92)90046-D
ISSN: 0010-4485
eISSN: 1879-2685
Publisher: Elsevier Science
Language: English
Date published: 1992
Academic Unit: Molecular Physiology and Biophysics
Record Identifier: 9984302191102771

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