Journal article
Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units
IEEE transactions on very large scale integration (VLSI) systems, Vol.9(5), pp.679-689
2001
DOI: 10.1109/92.953501
Abstract
We propose a resynthesis method that modifies a given circuit to reduce the number of paths in the circuit and thus improve its path delay fault testability. The resynthesis procedure is based on replacing subcircuits of the given circuit by structures called comparison units. A subcircuit can be replaced by a comparison unit if it implements a function belonging to the class of comparison functions defined here. Comparison units are fully testable for stuck-at faults and for path delay faults. In addition, they have small numbers of paths and gates. These properties make them effective building blocks for resynthesis to improve the path delay fault testability of a circuit. Experimental results demonstrate considerable reductions in the number of paths and increased path delay fault testability. These are achieved without increasing the number of gates, or the number of gates along the longest path in the circuit. The random pattern testability for stuck-at faults remains unchanged.
Details
- Title: Subtitle
- Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units
- Creators
- Irith Pomeranz - Purdue University West LafayetteSudhakar M Reddy - University of Iowa
- Resource Type
- Journal article
- Publication Details
- IEEE transactions on very large scale integration (VLSI) systems, Vol.9(5), pp.679-689
- DOI
- 10.1109/92.953501
- ISSN
- 1063-8210
- eISSN
- 1557-9999
- Publisher
- Institute of Electrical and Electronics Engineers
- Language
- English
- Date published
- 2001
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197223302771
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