Journal article
Robust Fault Models Where Undetectable Faults Imply Logic Redundancy
IEEE transactions on very large scale integration (VLSI) systems, Vol.18(8), pp.1230-1234
08/2010
DOI: 10.1109/TVLSI.2009.2020592
Abstract
We define a robust fault model as a model where the existence of an undetectable fault implies the existence of logic redundancy. The stuck-at fault model is robust, but other fault models such as certain bridging and interconnect open fault models are not. A robust fault model provides a mechanism to synthesize circuits in which all the target faults are detectable and 100% fault coverage is achievable. This is important since it provides a direct link between test quality and the circuit synthesis. We discuss robust fault models for bridging faults and interconnect open faults, and their use as part of a test generation process for a non-robust fault model.
Details
- Title: Subtitle
- Robust Fault Models Where Undetectable Faults Imply Logic Redundancy
- Creators
- Irith Pomeranz - Purdue University West LafayetteSudhakar M Reddy - University of Iowa
- Resource Type
- Journal article
- Publication Details
- IEEE transactions on very large scale integration (VLSI) systems, Vol.18(8), pp.1230-1234
- DOI
- 10.1109/TVLSI.2009.2020592
- ISSN
- 1063-8210
- eISSN
- 1557-9999
- Publisher
- IEEE
- Language
- English
- Date published
- 08/2010
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197068202771
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