Journal article
SPADES-ACE: A simulator for path delay faults in sequential circuits with extensions to arbitrary clocking schemes
IEEE transactions on computer-aided design of integrated circuits and systems, Vol.13(2), pp.251-263
02/1994
DOI: 10.1109/43.259948
Abstract
Testing of synchronous sequential circuits for path delay faults requires two sequences: a test sequence, that specifies the input values, and a clocking scheme, that specifies at what time units a fast clock should be applied. In this work, a fault simulator for path delay faults in synchronous sequential circuits is described, that has the following novel features. (1) For a given test sequence, all clocking schemes that have a single fast clock are simulated in parallel. (2) During the simulation process, it is possible to determine a minimal set of clocking schemes to achieve the same fault coverage as in (1). (3) Alternatively, it is possible to simulate the test sequence under a given clocking scheme, containing multiple fast clocks at arbitrary time units. (4) A path representation scheme is used, that allows efficient access to path delay faults detected by previous tests. Experimental results are presented to demonstrate these features and their effectiveness.< >
Details
- Title: Subtitle
- SPADES-ACE: A simulator for path delay faults in sequential circuits with extensions to arbitrary clocking schemes
- Creators
- I Pomeranz - University of IowaS.M Reddy - University of Iowa
- Resource Type
- Journal article
- Publication Details
- IEEE transactions on computer-aided design of integrated circuits and systems, Vol.13(2), pp.251-263
- Publisher
- IEEE
- DOI
- 10.1109/43.259948
- ISSN
- 0278-0070
- eISSN
- 1937-4151
- Language
- English
- Date published
- 02/1994
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197447402771
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