Journal article
Scan-BIST based on transition probabilities for circuits with single and multiple scan chains
IEEE transactions on computer-aided design of integrated circuits and systems, Vol.25(3), pp.591-596
03/2006
DOI: 10.1109/TCAD.2005.854634
Abstract
It is demonstrated that it is possible to generate a deterministic test set that detects all the detectable single stuck-at faults in a full-scan circuit such that each test vector contains a small number of transitions from 0 to 1 or from 1 to 0 when considering consecutive input values. Using this result, it is shown that built-in test-pattern generation for scan circuits can be based on transition probabilities, instead of probabilities of specific bits in the test set being 0 or 1. The resulting approach associates only two parameters with every set of test vectors: an initial value and a transition probability. It is demonstrated that this approach is effective in detecting all the detectable single stuck-at faults in benchmark circuits. The case where the circuit has a single scan chain, and the case where the circuit has multiple scan chains are considered.
Details
- Title: Subtitle
- Scan-BIST based on transition probabilities for circuits with single and multiple scan chains
- Creators
- Irith Pomeranz - Purdue University West LafayetteSudhakar M Reddy - University of Iowa
- Resource Type
- Journal article
- Publication Details
- IEEE transactions on computer-aided design of integrated circuits and systems, Vol.25(3), pp.591-596
- DOI
- 10.1109/TCAD.2005.854634
- ISSN
- 0278-0070
- eISSN
- 1937-4151
- Publisher
- IEEE
- Language
- English
- Date published
- 03/2006
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197343502771
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