Journal article
Static test compaction for diagnostic test sets of full-scan circuits
IET computers & digital techniques, Vol.4(5), pp.365-373
2010
DOI: 10.1049/iet-cdt.2009.0110
Abstract
The authors describe a static test compaction procedure for diagnostic test sets of full-scan circuits. Similar to reverse order and random order fault simulation procedures applied to fault detection test sets, the procedure simulates the test set in different orders in order to identify unnecessary tests. Two features distinguish the procedure from earlier ones. (i) It uses a diagnostic fault simulation process based on equivalence classes to identify tests that are not necessary for distinguishing fault pairs. (ii) It includes an iterative reordering process whose goal is to increase the number of tests that will be identified as unnecessary. Experimental results are presented to demonstrate the ability of the procedure to compact diagnostic test sets and the effectiveness of the iterative reordering process. © 2010 The Institution of Engineering and Technology.
Details
- Title: Subtitle
- Static test compaction for diagnostic test sets of full-scan circuits
- Creators
- I Pomeranz - Purdue University West LafayetteS. M Reddy - University of Iowa
- Resource Type
- Journal article
- Publication Details
- IET computers & digital techniques, Vol.4(5), pp.365-373
- DOI
- 10.1049/iet-cdt.2009.0110
- ISSN
- 1751-8601
- eISSN
- 1751-861X
- Publisher
- Institution of Engineering and Technology
- Language
- English
- Date published
- 2010
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197417402771
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