Journal article
Techniques for minimizing power dissipation in scan and combinational circuits during test application
IEEE transactions on computer-aided design of integrated circuits and systems, Vol.17(12), pp.1325-1333
1998
DOI: 10.1109/43.736572
Abstract
Reduction of power dissipation during test application is studied for scan designs and for combinational circuits tested using built-in self-test (BIST). The problems are shown to be intractable. Heuristics to solve these problems are discussed. We show that heuristics with good performance bounds can be derived for combinational circuits tested using BIST. Experimental results show that considerable reduction in power dissipation can be obtained using the proposed techniques. © 1998 IEEE.
Details
- Title: Subtitle
- Techniques for minimizing power dissipation in scan and combinational circuits during test application
- Creators
- Vinay Dabholkar - Silicon Autom. Syst., IndiaSreejit Chakravarty - IntelIrith Pomeranz - University of IowaSudhakar Reddy - University of Iowa
- Resource Type
- Journal article
- Publication Details
- IEEE transactions on computer-aided design of integrated circuits and systems, Vol.17(12), pp.1325-1333
- DOI
- 10.1109/43.736572
- ISSN
- 0278-0070
- eISSN
- 1937-4151
- Publisher
- Institute of Electrical and Electronics Engineers
- Language
- English
- Date published
- 1998
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197232602771
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