Test procedures for a class of pattern-sensitive faults in semiconductor random-access memories

D S Suk; S M Reddy

doi:10.1109/TC.1980.1675601

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Test procedures for a class of pattern-sensitive faults in semiconductor random-access memories

Journal article

Peer reviewed

Test procedures for a class of pattern-sensitive faults in semiconductor random-access memories

D S Suk and S M Reddy

IEEE transactions on computers, Vol.C-29(6), pp.419-429

06/01/1980

DOI: 10.1109/TC.1980.1675601

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Abstract

A class of pattern-sensitive faults in semiconductor random-access read/write memories are studied. A fault model is proposed and bounds on algorithms are derived. Efficient test procedures for detecting and locating modeled faults are developed, and lower bounds on the number of operations required in these procedures are given.

Details

Title: Subtitle: Test procedures for a class of pattern-sensitive faults in semiconductor random-access memories
Creators: D S Suk
S M Reddy
Resource Type: Journal article
Publication Details: IEEE transactions on computers, Vol.C-29(6), pp.419-429
DOI: 10.1109/TC.1980.1675601
ISSN: 0018-9340
eISSN: 1557-9956
Language: English
Date published: 06/01/1980
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197324802771

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