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Testable realizations for FET stuck-open faults in CMOS combinational logic circuits
Journal article   Peer reviewed

Testable realizations for FET stuck-open faults in CMOS combinational logic circuits

S. M Reddy and M. K Reddy
IEEE transactions on computers, Vol.35(8), pp.742-754
1986
DOI: 10.1109/TC.1986.1676825

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Abstract

Applied Sciences Circuit properties Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology

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