Theorems for identifying undetectable faults in partial-scan circuits

Irith Pomeranz; Sudhakar M Reddy

doi:10.1109/TCAD.2003.814957

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Theorems for identifying undetectable faults in partial-scan circuits

Journal article

Peer reviewed

Theorems for identifying undetectable faults in partial-scan circuits

Irith Pomeranz and Sudhakar M Reddy

IEEE transactions on computer-aided design of integrated circuits and systems, Vol.22(8), pp.1092-1097

08/2003

DOI: 10.1109/TCAD.2003.814957

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Abstract

We provide a definition of undetectable faults in partial-scan circuits under a test application scheme where a test consists of primary input vectors applied at-speed between scan operations. We also provide sufficient conditions for a fault to be undetectable under this test application scheme. We present experimental results on finite-state machine benchmarks to demonstrate the effectiveness of these conditions in identifying undetectable faults.

Benchmark testing

Circuit faults

Circuit simulation

Circuit testing

Computational modeling

Fault diagnosis

Flip-flops

Logic arrays

Logic circuits

Sufficient conditions

Details

Title: Subtitle: Theorems for identifying undetectable faults in partial-scan circuits
Creators: Irith Pomeranz - Purdue University West Lafayette
Sudhakar M Reddy
Resource Type: Journal article
Publication Details: IEEE transactions on computer-aided design of integrated circuits and systems, Vol.22(8), pp.1092-1097
DOI: 10.1109/TCAD.2003.814957
ISSN: 0278-0070
eISSN: 1937-4151
Publisher: IEEE
Language: English
Date published: 08/2003
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197203602771

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