Journal article
Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis
International journal of parallel programming, Vol.38(3-4), pp.185-202
01/01/2010
DOI: 10.1007/s10766-009-0124-7
Abstract
Efficient utilization of the inherent parallelism of multi-core architectures is a grand challenge in the field of electronic design automation (EDA). One EDA algorithm associated with a high computational cost is automatic test pattern generation (ATPG). We present the ATPG tool TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully chosen mix of various optimization techniques, multi-million-gate industrial circuits are handled without aborts. TIGUAN supports both conventional single-stuck-at faults and sophisticated conditional multiple stuck-at faults which allows to generate patterns for non-standard fault models. We demonstrate how TIGUAN can be combined with conventional structural ATPG to extract full benefit of the intrinsic strengths of both approaches.
Details
- Title: Subtitle
- Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis
- Creators
- Alexander Czutro - Computer Architecture Group, Institute for Computer Science, Albert-Ludwigs-UniversityIlia Polian - Albert-Ludwigs-UniversityMatthew Lewis - University of FreiburgPiet Engelke - Albert-Ludwigs-UniversitySudhakar M Reddy - University of IowaBernd Becker - Albert-Ludwigs-University
- Resource Type
- Journal article
- Publication Details
- International journal of parallel programming, Vol.38(3-4), pp.185-202
- DOI
- 10.1007/s10766-009-0124-7
- ISSN
- 0885-7458
- eISSN
- 1573-7640
- Publisher
- Springer US
- Language
- English
- Date published
- 01/01/2010
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197355002771
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