Journal article
Universal delay test sets for logic networks
IEEE transactions on very large scale integration (VLSI) systems, Vol.7(2), pp.156-166
1999
DOI: 10.1109/92.766742
Abstract
It has been shown earlier that, if we are restricted to unate gate network (UGN) realizations, there exist universal test sets for Boolean functions. Such a test set only depends on the function f, and checks any UGN realization of f for all multiple stuck-at faults and all robustly testable stuck-open faults. In this paper, we prove that these universal test sets are much more powerful than implied by the above results. They also constitute complete delay fault test sets for arbitrary UGN implementations of a given function. This is even true for UGN networks which are not completely testable with respect to the gate or path delay fault model. Our ability to prove the temporal correctness of such circuit realizations comes from the fact that we do not argue the correctness of individual paths, but rather complete path systems.
Details
- Title: Subtitle
- Universal delay test sets for logic networks
- Creators
- Uwe Sparmann - Laboratoire d'Informatique de Paris-NordHolger Müller - Saarland UniversitySudhakar M Reddy - University of Iowa
- Resource Type
- Journal article
- Publication Details
- IEEE transactions on very large scale integration (VLSI) systems, Vol.7(2), pp.156-166
- Publisher
- Institute of Electrical and Electronics Engineers
- DOI
- 10.1109/92.766742
- ISSN
- 1063-8210
- eISSN
- 1557-9999
- Language
- English
- Date published
- 1999
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197430002771
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